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nt68p62 -01 8-bit microcontroller for monitor (32k otp rom type) 1 v2. 2 features n operating voltage range: 4.5v to 5.5v n cmos technology for low power consumption n 6502 8-bit cmos cpu core n 8 mhz operation frequency n 32k bytes of otp (one time programming) rom n 512 bytes of ram n one 8-bit base timer n 13 channels of 8-bit pwm outputs with 5v open drain n 4 channel a/d converters with 6-bit resolution n 25 bi-directional i/o port pins (8 dedicated i/o pins) n hsync/vsync signals processor for separate & composite signal, including hardware sync signals polarity detection and freq. counters with 2 sets of hsync counting interval n hsync/vsync polarity controlled output, 5 selectable free run output signals and self-test patterns, auto- mute function, half freq. i/o function n t wo built-in i 2 c bus interfaces support vesa ddc1/2b+ n two layers of interrupt management nmi interrupt sources - inte0 (external int with selectable edge trigger) - intmute (auto mute activated) irq interrupt sources - ints0/1 ( scl go-low int) - inta0/1 (slave address matched int) - inttx0/1 (shift register int) - intrx0/1 (shift register int) - intnak0/1 (no acknowledge) - intstop0/1 (stop condition occurred int) - inte1 (external int with selectable edge trigger) - intv (vsync int) - intmr (base timer int) - intadc ( ad conversion done int) n hardware watch-dog timer function n 40-pin p-dip and 42-pin s-dip packages general description the nt68p62 is a new generation of monitor m c for auto- sync and digital control applications. particularly, this chip supports various and efficient functions to allow users to easily develop usb monitors. it contains the 6502 8-bit cpu core, 512 bytes of ram used as working ram and stack area, 32k bytes of otp rom, 13-channel of 8-bit pwm d/a converters, 4-channel a/d converters for keys detection which can save i/o pins, one 8-bit pre-loadable base timer, internal hsync and vsync signals processor, and a watch-dog timer which prevents the system from abnormal operation and two i 2 c bus interface. the user can store edid data in the 128 bytes of ram for ddc1/2b, so that user can reduce a dedicated eeprom for edid. and half frequency output function can save external one- shot circuit. all of these designs are committed to offer our user saving component cost. the 42 pin s-dip ic provides two additional i/o pins ? port40 & port41, part number nt68p62u represents the s-dip ic. for future reference, port40 & port42 is only available for the 42 pin s-dip ic.
nt68p62 -01 2 pin configurations 40-pin p-dip [pgm] dac2 dac1/adc3 [oe] dac0/adc2 [db7] p27 [vpp] reset v dd gnd osco osci [ce] p14/pattern [a10] p12/halfo [a9] p11/adc1 [a8] p10/adc0 p20 [db0] p07/hsynco [a7] p31/scl0 [a13] dac4/scl1 [mode1] dac3 [mode0] hsynci vsynci/intv [a14] nt68p62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p15/inte0 [a11] p13/halfi p16/inte1 17 18 19 20 24 23 22 21 dac5/sda1 [mode2] dac6 [reset] creg p21 [db1] p22 [db2] p06/vsynco [a6] p05/dac12 [a5] p04/dac11 [a4] p03/dac10 [a3] p02/dac9 [a2] p01/dac8 [a1] p00/dac7 [a0] p30/sda0 [a12] [db6] p26 [db5] p25 [db4] p24 [db3] p23 * [ ]: otp mode 42-pin s-dip [pgm] dac2 dac1/adc3 [oe] dac0/adc2 [vpp] reset v dd p40 gnd osco osci p15/inte0 [a11] p13/halfi [a9] p11/adc1 [a8] p10/adc0 p00/dac7 [a0] p16/inte1 p01/dac8 [a1] p02/dac9 [a2] p03/dac10 [a3] p04/dac11 [a4] p06/vsynco [a6] p07/hsynco [a7] dac6 [reset] p41 dac5/sda1 [mode2] dac4/scl1 [mode1] dac3 [mode0] hsynci vsynci/intv [a14] creg nt68p62u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 [ce] p14/pattern [a10] p12/halfo [db7] p27 [db6] p26 [db5] p25 [db4] p24 [db3] p23 17 18 19 20 21 p05/dac12 [a5] p31/scl0 [a13] p30/sda0 [a12] p20 [db0] p21 [db1] p22 [db2] 26 25 24 23 22 * [ ]: otp mode block diagram timing generator cpu core 6502 interrupt controller h/v sync signals processor sram + stack 512 bytes watch dog timer pwm dacs i/o ports osci osco v dd gnd hsynci inte0/1 scl0 sda0 dac0 - dac7 p00 - p07 p10 - p16 p30 - p31 vsynco a/d converter adc0 - adc3 8-bit base timer p40 - p41 iic bus p20 - p27 hsynco halfi halfo dac8 - dac12 vsynci/intv otp program rom 32k bytes pattern scl1 sda1 voltage regulator creg
nt68p62 -01 3 pin description pin no. 40 pin 42 pin designation reset init. i/o description 1 1 dac2 [ pgm ] o [ i ] open drain 5v, d/a converter output 2 [otp rom program control] 2 2 dac1/adc3 dac1 o open drain 5v, d/a converter output 1, shared with a/d converter channel 3 input 3 3 dac0/adc2 [ oe ] dac0 o open drain 5v, d/a converter output 0, shared with a/d converter channel 2 input [otp rom program output enable] 4 4 reset [ vpp ] i [ p ] schmitt trigger input pin, low active reset with internal pulled down 50k w register * [otp rom program supply voltage] 5 5 v dd p power 6 7 gnd p ground 7 8 osco o crystal osc output 8 9 osci i crystal osc input 9 10 p15/inte0 i/o bi-directional i/o pin with internal pulled up 22k w register, shared with input pin of external interrupt source0 (nmi), with schmitt trigger, selectable triggered, and internal pulled up 22k w register 10 11 p14/pattern [ a15/ce ] i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with the output of self test pattern [ otp rom program address buffer & chip enable ] 11 12 p13/halfi [ a11 ] p13 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with half hsync input, shared with a/d converter channel 3 input [ otp rom program address buffer ] 12 13 p12/halfo [ a10 ] p12 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with half hsync output [ otp rom program address buffer ] 13 14 p11/adc1 [ a9 ] p11 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with a/d converter channel 1 input [ otp rom program address buffer ] 14 15 p10/adc0 [ a8 ] p10 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with a/d converter channel 0 input [ otp rom program address buffer ] 15 16 p16/inte1 p16 i/o bi-directional i/o pin with internal pulled up 22k w register, shared with input pin of external interrupt source1, with schmitt trigger, selectable triggered, and an internal pulled up 22k w register
nt68p62 -01 4 pin description (continued) pin no. 40 pin 42 pin designation reset init. i/o description 16 - 23 17 - 24 p27 ? p20 [ db7 ] ? [ db0] i/o [ i/o ] bi-directional i/o pin, push-pull structure with high current drive/sink capability [ otp rom program data buffer ] 24 25 p30/sda0 [ a12 ] p30 i/o [ i ] open drain 5v bi-directional i/o pin p30, shared with sda0 pin of i 2 c bus schmitt trigger buffer [ otp rom program address buffer ] 25 26 p31/scl0 [ a13 ] p31 i/o [ i ] open drain 5v bi-directional i/o pin p31, shared with scl0 pin of i 2 c bus schmitt trigger buffer [ otp rom program address buffer ] 26 27 p00/dac7 [ a0 ] p00 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with open drain 5v d/a converter output 8 [ otp rom program address buffer ] 27 28 p01/dac8 [ a1 ] p01 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with open drain 5v d/a converter output 9 [ otp rom program address buffer ] 28 29 p02/dac9 [ a2 ] p02 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with open drain 5v d/a converter output 10 [ otp rom program address buffer ] 29 30 p03/dac10 [ a3 ] p03 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with open drain 5v d/a converter output 11 [ otp rom program address buffer ] 30 31 p04/dac11 [ a4 ] p04 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with open drain 5v d/a converter output 12 [ otp rom program address buffer ] 31 32 p05/dac12 [ a5 ] p05 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with open drain 5v d/a converter output 13 [ otp rom program address buffer ] 32 33 p06/vsynco [ a6 ] p06 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with vsync out [ otp rom program address buffer ] 33 34 p07/hsynco [ a7 ] p07 i/o [ i ] bi-directional i/o pin with internal pulled up 22k w register, shared with hsync out [ otp rom program address buffer ] 34 35 creg o on chip voltage regulator output, external regulating cap.( 10 f ~ 1 0 0f) should be connected here 35 36 dac6 [ reset ] o [ i ] open drain 5v, d/a converter output 6 [ otp rom reset ] 36 38 dac5/sda1 [ mode2 ] o [ i ] open drain 5v, d/a converter output 5, shared with open drain sda1 line of i 2 c bus, schmitt trigger buffer [ otp rom mode select ]
nt68p62 -01 5 pin description (continued) pin no. designation reset init. i/o description 40 pin 42 pin 37 39 dac4/scl1 [ mode1 ] o [ i ] open drain 5v, d/a converter output 4, shared with open drain scl1 line of i 2 c bus, schmitt trigger buffer [ otp rom mode select ] 38 40 dac3 [ mode0 ] o [ i ] open drain 5v, d/a converter output 3 [ otp rom mode select ] 39 41 hsynci i debouncing & schmitt trigger input pin for video horizontal sync signal, internal pull high, shared with composite sync input 40 42 vsynci/intv [ a14 ] vsynci i [ i ] debouncing & schmitt trigger input pin for video vertical sync signal, internal pull high, shared with input pin of external interrupt source intv with schmitt trigger, selectable triggered, and internal pulled up 22k w register [ otp rom program address buffer ] - 6 p40 i/o bi-directional i/o pin with internal pulled up 22k w register, only 42 pin s-dip available - 37 p41 i/o bi-directional i/o pin with internal pulled up 22k w register, only 42 pin s-dip available * this reset pin must be pulled high by external pulled-up register (5k w suggestion), or it will remain in low voltage to continually rest system.
nt68p62 -01 6 functional description 1. 6502 cpu the 6502 is an 8-bit cpu that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory ranges, and interrupt input options. the cpu clock cycle is 4mhz (8mhz system clock divided by 2). please refer to the 6502 data sheet for more detailed information. accumnlator a index register y 0 7 7 index register x 7 0 0 stack pointer sp 0 status register p 0 7 carry zero irq disable decimal mode brk command overflow negative figure 1.1. the 6502 cpu registers and status flags 7 program counter pch 8 15 7 0 pcl 1=true 1=result zero 1=disable 1=true 1=neg 1=true 1=brk n v c z i d b
nt68p62 -01 7 2. instruction set list instruction code meaning operation adc add with carry a + m + c ? a, c and logical and a ?e m ? a asl shift left one bit c ?? m7 ? m0 ?? 0 bcc branch if carry clears branch on c ? 0 bcs branch if carry sets branch on c ? 1 beq branch if equal to zero branch on z ? 1 bit bit test a ?e m, m7 ? n, m6 ? v bmi branch if minus branch on n ? 1 bne branch if not equal to zero branch on z ? 0 bpl branch if plus branch on n ? 0 brk break forced interrupt pc+2 ?? pc ?? bvc branch if overflow clears branch on v ? 0 bvs branch if overflow sets branch on v ? 1 clc clear carry 0 ? c cld clear decimal mode 0 ? d cli clear interrupt disable bit 0 ? i clv clear overflow 0 ? v cmp compare accumulator to memory a ?e m cpx compare with index register x x ?e m cpy compare with index register y y ?e m dec decrement memory by one m ?e 1 ? m dex decrement index x by one x ?e 1 ? x dey decrement index y by one y ?e 1 ? y eor logical exclusive-or a ? m ? a inc increment memory by one m + 1 ? m inx increment index x by one x + 1 ? x iny increment index y by one y + 1 ? y
nt68p62 -01 8 instruction set list (continued) instruction code meaning operation jmp jump to new location (p c +1) ? p cl, (p c +2) ? p ch jsr jump to subroutine p c +2 ?? , (p c +1) ? p cl, (p c +2) ? p ch lda load accumulator with memory m ? a ldx load index register x with memory m ? x ldy load index register y with memory m ? y lsr shift right one bit 0 ? m7 ? m0 ? c nop no operation no operation (2 cycles) ora logical or a + m ? a pha push accumulator on stack a ?? php push status register on stack p ?? pla pull accumulator from stack a ?? plp pull status register from stack p ?? rol rotate left through carry c ?? m7 ? m0 ?? c ror rotate right through carry c ? m7 ? m0 ? c rti return from interrupt p ?? , pc ?? rts return from subroutine pc ?? , pc+1 ? pc sbc subtract with borrow a ?e m ?e c ? a, c sec set carry 1 ? c sed set decimal mode 1 ? d sei set interrupt disable status 1 ? i sta store accumulator in memory a ? m stx store index register x in memory x ? m sty store index register y in memory y ? m tax transfer accumulator to index x a ? x tay transfer accumulator to index y a ? y tsx transfer stack pointer to index x s ? x txa transfer index x to accumulator x ? a txs transfer index x to stack pointer x ? s tya transfer index y to accumulator y ? a * refer to 6502 programming data book for more details.
nt68p62 -01 9 3. ram: 512 x 8 bits the built-in 512 x 8-bit sram is used for data memory and stack area. the ram addressing range is from $0080 to $027f. the contents of ram are undetermined at power-up and are not affected by system reset. software programmers can allocate stack area in the ram by setting stack pointer register (s). because the 6502 default stack pointer is $01ff, programmers must set s register to ffh when starting the program. as; ldx #$ff txs ram unused rom $0000 $0080 $8000 $ffff stack pointer $fffe $fffd $fffc rst-l rst-h irq-l irq-h reset vector irq vector $027f $0280 ( 32 k bytes ) otp $003d system registers unused $7fff ( 512 bytes ) $fffb $fffa nmi-l nmi-h nmi vector $01ff 4. rom: 32k x 8 bits nt68p62 provides 32k rom space for programming. the rom space is located from $8000 to $ffff. the addresses, from $fffa to $ffff, are reserved for the 6502 cpu vectors, thus users must arrange them by themselves.
nt68p62 -01 10 5. system registers addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w control registers for i/o port0 & port1 $0000 pt0 ffh p07 p06 p05 p04 p03 p02 p01 p00 rw $0001 pt1 7fh - p16 p15 p14 p13 p12 p11 p10 rw control register to control port2 i/o direction $0002 pt2dir ffh p27oe p26oe p25oe p24oe p23oe p22oe p21oe p20oe w control registers for i/o port2 - 4 $0003 pt2 ffh p27 p26 p25 p24 p23 p22 p21 p20 rw $0004 pt3 03h - - - - - - p31 p30 rw $0005 pt4 03h only available for the 42 pin sdip version - p41 p40 rw control registers for synprocessor ffh - - - - insen - hsel s/ c r $0006 syncon ffh - - - - insen enhsel hsel s/ c w ffh - - hsynci vsynci hpoli vpoli hpolo vpolo r $0007 hv con ffh enhout enhout - - - - hpolo vpolo w $0008 hcnt l 00h hcl7 hcl6 hcl5 hcl4 hcl3 hcl2 hcl1 hcl0 r hcntov - - - hch3 hch2 hch1 hch0 r $0009 hcnt h 00h clrhov - - - - - - - w $000a vcnt l 00h vcl7 vcl6 vcl5 vcl4 vcl3 vcl2 vcl1 vcl0 r vcntov - vch5 vch4 vch3 vch2 vch1 vch0 r $000b vcnt h 00h clrvov - - - - - - - w $000c freecon ffh enpat pat1 - - - freq2 freq1 freq0 w $000d halfcon ffh enhalf nohalf halfpol - - - - - w $000e automute ffh enhdiff enpol enover - hdiffvl3 hdiffvl2 hdiffvl1 hdiffvl0 w control registers to enable pwm 8 - 15 channels $000f endac ffh - - endk12 endk11 endk10 endk9 endk8 endk7 w control registers for adc 0 - 3 channels $0010 enadc ffh csta - - - enadc3 enadc2 enadc1 enadc0 w $0011 ad0 reg c0h - - ad05 ad04 ad03 ad02 ad01 ad00 r $0012 ad1 reg 00h - - ad15 ad14 ad13 ad12 ad11 ad10 r $0013 ad2 reg 00h - - ad25 ad24 ad23 ad22 ad21 ad20 r $0014 ad3 reg 00h - - ad35 ad34 ad33 ad32 ad31 ad30 r
nt68p62 -01 11 system registers (continued) addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w control register for polling (read) interrupt groups & clearing (write) inte0 & intmute interrupt requests - - - - - - inte0 intmute r $0016 nmipoll 00h - - - - - - clre0 clrmute w $0017 irqpoll 00h - - - - - irq2 irq1 irq0 r control registers of interrupt enable $0018 ienmi 00h - - - - - - inte0 intmute rw $0019 ieirq0 00h - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 rw $001a ieirq1 00h - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 rw $001b ieirq2 00h - - - - intadc intv inte1 intmr rw control registers for polling (read) & clearing (write) interrupt requests - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 r $001c irq0 00h - - clrs0 clra0 clrtx0 clrrx0 clrnak0 clrstop0 w - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 r $001d irq1 00h - - clrs1 clra1 clrtx1 clrrx1 clrnak1 clrstop1 w - - - - intadc intv inte1 intmr r $001e irq2 00h - - - - clradc clrv clre1 clrmr w selection of edge triggered for intv, inte0 & 1 interrupts $001f trigger ffh - - - - - intvr inte1r inte0r r/w control registers for clearing watch dog timer $0020 clr wdt - 0 1 0 1 0 1 0 1 w control register for ddc1/2b+ of channel 0 $0021 ch0addr a0h adr7 adr6 adr5 adr4 adr3 adr2 adr1 - w $0022 ch0txdat 00h tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 w $0023 ch0rxdat 00h rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 r e0h enddc md1/ 2 - start stop - txack - w $0024 ch0con - - srw start stop - - - r $0025 ch0clk ffh mode mrw rstart - - ddc2br2 ddc2br1 ddc2br0 w control register for ddc1/2b+ of channel 1 $0026 ch1addr a0h adr7 adr6 adr5 adr4 adr3 adr2 adr1 - w $0027 ch1txdat 00h tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 w $0028 ch1rxdat 00h rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 r
nt68p62 -01 12 system registers (continued) addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w enddc md1/ 2 - start stop - txack - w $0029 ch1con e0h - - srw start stop - - - r $002a ch1clk ffh mode mrw rstart - - ddc2br2 ddc2br1 ddc2br0 w control registers for base timer $002e bt 00h bt7 bt6 bt5 bt4 bt3 bt2 bt1 bt0 w $002f btcon 03h - - - - - - btclk enbt w control registers for pwm channel 0 - 13 $0030 dach0 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0031 dach1 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0032 dach2 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0033 dach3 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0034 dach4 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0035 dach5 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0036 dach6 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0037 - - - - - - - - - $0038 dach7 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0039 dach8 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003a dach9 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003b dach10 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003c dach11 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003d dach12 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw
nt68p62 -01 13 6. timing generator this block generates the system timing and control signal to be supplied to the cpu and on-chip peripherals. a crystal quartz, ceramic resonator, or an external clock signal which will be provided to the osci pin generates system timing. it generates 8mhz system clock, 4mhz for the cpu. although internal circuits have a feedback resister and compacitor included, users can externally add these components for proper operating. the typical clock frequency is 8mhz. different frequencies will affect the operation of those on-chip peripherals whose operating frequency is based on the system clock. 8mhz osci osco nt68p62 osci nt68p62 figure 6.1. oscillator connections (1) (2) unconnected external clock osco 7. reset the nt68p62 can be reset by the external reset pin or by the internal watch-dog timer. this is used to reset or start the microcontroller from a power down condition. during the time that this reset pin is held low (*reset line must be held low for at least two cpu clock cycles), writing to or from the m c is inhibited. when a positive edge is detected on the reset input, the m c will immediately begin the reset sequence. after a system initialization time of six cpu clock cycles, the mask interrupt flag will be set and the m c will load the program counter from the memory vector locations $fffc and $fffd. this is the start location for program control. an internal schmitt trigger buffer at the reset pin is provided to improve noise immunity. the reset status is as follows: 1. p ort 0 ?b p ort1 ?b port2 ?b port3 ( & port4) pins will act as i/o ports with high output 2. sync processor counters rese t and vcnt | hcnt latches cleared 3. all sync outputs are disabled 4. base timer is disabled and cleared 5. various interrupt sources are disabled and cleared 6. a/d converter is disabled and stopped 7. ddc 1/2b+ function is disabled 8. pwm dac0 ? dac6 output 50% duty waveform and dac7 - dac12 is disabled 9. watch-dog timer is cleared and enabled
nt68p62 -01 14 8. a/d converters the structure of these analog to digital converters is 6-bit successive approximation. analog voltage is supplied from external sources to the a/d input pins and the result of the conversion is stored in the 6-bit data latch registers ($0011 & $0014). the a/d channels are activated by clearing the correspondent control bits in the enadc control register. when users write '0' into one of the enable control bits, its correspondent i/o pin or dac will be switched to the a/d converter input pin (adc0 & adc1 shared with port10 & port 11; adc2 & adc3 shared wit dac0 & dac1). conversion will be started by clearing csta bit (conversion start) in the enadc control register. when conversion is finished, system will set this intadc bit. users can monitor this bit to get the valid a/d conversion data in the ad latch registers ($0011 - $0014). users can also open interrupt sources to remind users to get the stable digital data. notice that only at the activated a/d channel, its latched data are available. the analog voltage to be measured should be stabled during the conversion operation and the variation will not exceed lsb for the best accuracy in measurement. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $0010 enadc ffh csta - - - enadc3 enadc2 enadc1 enadc0 w $0011 ad0 reg c0h - - ad05 ad04 ad03 ad02 ad01 ad00 r $0012 ad1 reg 00h - - ad15 ad14 ad13 ad12 ad11 ad10 r $0013 ad2 reg 00h - - ad25 ad24 ad23 ad22 ad21 ad20 r $0014 ad3 reg 00h - - ad35 ad34 ad33 ad32 ad31 ad30 r $001b ieirq2 00h - - - - intadc intv inte1 intmr r/w $001e irq2 00h - - - - intadc intv inte1 intmr r - - - - clradc clrv clre1 clrmr w reference adc table (v dd = 5.0v) 15 1.50v 1c 2.06v 23 2.59v 2a 3.14v 16 1.58v 1d 2.12v 24 2.67v 2b 3.22v 17 1.66v 1e 2.20v 25 2.75v 2c 3.30v 18 1.74v 1f 2.28v 26 2.82v 2d 3.38v 19 1.82v 20 2.35v 27 2.91v 2e 3.46v 1a 1.90v 21 2.44v 28 2.98v 2f 3.54v 1b 1.98v 22 2.51v 29 3.07v 30 3.62v note: it is strongly recommended that the adc ? s input signal should be allocated in the adc ? s linear voltage range (1.5v~3.5v) to obtain a stable digital value. do not use the outer ranges (0v~1.4v & 3.6v~5.0v) in which the converted digital value is not guaranteed.
nt68p62 -01 15 9. pwm dacs (pulse width modulation d/a converters) there are 13 pwm d/a converters with 8-bit resolution in nt68p62. all of these d/a (dac0 - dac12) converters are open- drain output structure with external 5v applied maximum. dac0 ? dac6 are dedicated pwm channels, and dac7 - dac12 are shared with i/o pins. those shared pwm channels are activated by clearing the correspondent control bits in the endac control register ($000f). when users write '0' into one of the enable control bits, its correspondent i/o pin will be switched to pwm output pin. the pwm refresh rate is 62.5khz operating on 8mhz system clock. there are 13 readable dach registers corresponding to 13 pwm channels ($0030 - $003d). each pwm output pulse width is programmable by setting the 8 bit digital to the corresponding dach registers. when these dach registers are set to 00h, the dac will output low (gnd level) and every 1 bit addition will add 62.5ns pulse width. after reset, all dac outputs are set to 80h (1 /2 duty output). (please refer to figure 9.1 for the detailed timing diagram of pwm d/a output.) 01 02 m 255(ff) fosc 255 0 1 2 m 255 1 pwm value : 8mhz 00 figure 9.1. the dac output timing diagram and wave table 03 3 m-1 0
nt68p62 -01 16 pwm dacs (continued) dac0 & dac1 are shared with adc2 & adc3 input pins respectively. if enadc2/ 3 bit in the enadc control register is cleared to low, a/d converters will activate simultaneously. after the chip is reset, enadc2/ 3 bits will be in h igh state and dac0 & dac1 will act as pwm output pins. dac4 & dac5 are shared with scl1 & sda1 i/o pins respectively. if users clear the enddc bit in the ch1con control register to low, channel 1 of ddc will be activated. when used as ddc channel, the i/o port will be an open drain structure and include 'schmitt trigger' buffer for noise immunity. after the chip is reset, enddc bits will be in high state and dac4 - dac5 will act as pwm output pins. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $000f endac ffh - - endk12 endk11 endk10 endk9 endk8 endk7 w $0010 enadc ffh csta - - - enadc3 enadc2 enadc1 enadc0 w $0030 dach0 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0031 dach1 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0032 dach2 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0033 dach3 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0034 dach4 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0035 dach5 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0036 dach6 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0037 - - - - - - - - - $0038 dach7 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0039 dach8 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003a dach9 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003b dach10 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003c dach11 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $003d dach12 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw dac control register ($000f) and dac value register ($0030 - $003d)
nt68p62 -01 17 10. watch-dog timer (wdt) the nt68p62 implements a watch-dog timer reset to avoid system stop or malfunction. the clock of the wdt is from on-chip rc oscillator which does not require any external components. thus, the wdt will run, even if the clock on the osci/osco pins of the device have been stopped. the wdt time interval is about 0.5 second. the wdt must be cleared within every 0.5 second when the software is in normal sequence , otherwise the wdt will overflow and cause a reset. the wdt is cleared and enabled after the system is reset, and can not be disabled by the software. users can clear the wdt by writing 55h to clrwdt register ($0020). as; lda #$55 sta $0020 addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $0020 clr wdt - 0 1 0 1 0 1 0 1 w 11. interrupt controller the system provides two kinds of interrupt sources: nmi & irq. the nmi can not be masked and if enabling nmi interrupt sources, users will execute the nmi interrupt vector anytime when sources are activated. the irq interrupts can be masked by executing a cli instruction or setting the interrupt mask flag directly in the m c status register. in process irq interrupt, if the interrupt mask flag is not set, the m c will begin an interrupt sequence. the program counter and processor status register will be stored in the stack. the m c will then set the interrupt mask flag high so that no further interrupts may occur. at the end of this cycle, the program counter will be loaded from addresses $fffe & $ffff, then transferring program control to the memory vector located at these addresses. for nmi interrupt, m c will transfer execution sequence to the memory vector located at addresses $fffa & $fffb. when manipulating various interrupt sources, nt68p62 divides them into two groups for accessing them easily. one is nmi group and the other is irq group. - the nmi group includes inte0, intmute. - the irq group includes subgroup of irq0, irq1,rq2: i rq0: ddc1/2b+ channel 0 interrupt sources; it includes ints0, inta0, inttx0, intrx0, intnak0 and intstop0 interrupts. irq1: ddc1/2b+ channel 1 interrupt sources; it includes ints0, inta1, inttx1, intrx1, intnak1 and intstop1. irq2: it includes intadc, in tv, inte1 and intmr interrupt sources. below are the interrupt sources. nonmaskable interrupt group: interrupt meaning action inte0 int external 0 int it will be activated by the rising edge or falling edge of external interrupt pulse. the triggered edge can be selected by edge0 bit. intmute auto mute it will be activated when the mute condition occurres (hsync frequency change). please refer the synprocessor section for more detailed explanation. maskable interrupt group: interrupt meaning action intadc a/d converion done user activates the adc by clearing the cstart bit. when ad conversion is done, this bit will be set. intv int vsync int it will be activated as the rising edge of every vsync pulse. inte1 int external 1 int it will be activated by the rising edge or falling edge of external interrupt pulse. the triggered edge can be selected by edge1 bit. intmr int timer int it will be activated as the rising edge of every when the base timer counter overflows and counting from $ff to $00.
nt68p62 -01 18 ddc channel 0/1 maskable interrupt sources: interrupt meaning action ints int scl go-low int in ddc1 mode, it will be activated when the external device proceed a ddc2 communication. this action includes pull the scl line to ground or send out an 'start' condition directly. system will respond to this action by changing ddc1 mode to ddc2 slave mode. inta int address matched int it will be activated at ddc2 slave mode when the external device call nt68p62 slave address. if this calling address matches the nt68p62 address, system will generate this interrupt to remind user inttx int transfer buffer empty int it will be activated at ddc2 mode when transmission buffer, iic_txdat, is empty at transmission mode. intrx int receiving buffer overflow int it will be activated at ddc2 mode when new data have store in the iic_rxdat register at receive mode. intnak int no acknowledge int at transmission mode, this interrupt will be activated when nt68p62 have send out one byte data but the external device does not respond an acknowledge bit to it. intstop int ddc2 stop int in slave mode, this interrupt will be activated when the nt68p62 receives an 'stop' condition. intstop0 intnak0 intrx0 inttx0 inta0 ints0 intstop1 intnak1 intrx1 inttx1 inta1 ints1 intmr inte1 intv intadc intmute inte0 irq0 irq (to cpu 6502) nmi (to cpu 6502) irq0 irq1 irq2 figure 11.1. interrupt controller structure irq1 irq2 ieirq0 ieirq1 ieirq2 nmipoll ienmi
nt68p62 -01 19 enabling interrupts: the system will disable all of these interrupts after reset. users can enable each of the interrupts by setting the interrupt enable bits at ienmi, ieirq0 - ieirq3 control registers. for example, if users want to enable external interrupt 0 (inte0), write '1' to inte0 bit in the ienmi control register. at the inte0 pin, whenever nt68p62 has detected an interrupt message, it will generate an interrupt sequence to fetch the nmi vector. because these iex control registers can be read, users can read back what interrupts he has been activated. at polling sequence, users need not poll those unactivated interrupts. requesting interrupts to be set: no matter user have been set the interrupt enable bits or not, if the interrupt triggered condition is matched, system will set the correspondent bits in the irq0 - irq3 control registers or in the nmipoll control register (inte0 & intmute bits). for example, if at vsynci pin, system have detected a pulse occurring, system will set the intv bit in the irq2 control register. interrupt groups: system divides irq interrupt sources into several groups, ex irq0, irq1, irq2 and irq3. at each of these groups, if its membership in the one of the interrupt groups have been activated, its group bit in the irqpoll control register will be set. for example, if the ints0 of the first ddc1/2b+ channel is activated, the ints0 bit in the irq0 will be set and the irq0 bit in the irqpoll control register also will be set. notice that the irq0 bit will be cleared by system when all of its membership of interrupt sources, ints0, inttx0, intrx0, intnak0 and intstop0 have been cleared by the user or system. the nmi group is also oprating the same procedure as irq groups. polling interrupts: when nmi interrupt occurrs, at nmi interrupt service routine, users must poll the inte0 & intmute bit in the nmipoll control register to confirm the nmi interrupt source. the polling sequence decides the priority of nmi interrupt acceptation. when irq interrupt occurrs, at irq interrupt service routine, users must poll the irq0 - irq3 in the irqpoll control register to confirm the irq interrupt source. in the same way, the polling sequence decides the priority of irq interrupt acception. when deciding the irq source, users can further confirm the real interrupt source by polling the correspondent irqx control register ($001c - $001e). clearing the interrupt request bit: when interrupt occurrs, the cpu will jump to the address defined by the interrupt vector to execute interrupt service routine. users can check which one of the interrupt sources is activated and operating a tast. it is that upon entering the interrupt service routine, the request bit that caused the interrupt must be cleared by user before finishing the service routine and returning to normal instruction sequence. if users forget to clear this request bit, after returning to main program, it will interrupt cpu again because the request bit remains activated. simply, users just need write '1' to the polling bits in the nmipoll & irqx registers ($0016 & $001c - $001e) to clear those completed interrupt sources. selecting interrupt triggered edge: at intv, inte0 & inte1 interrupt sources, these are now edge triggered type. system provides the selection of rising or falling edge triggered under user ? s control. after reset, the rising edge triggered are provided and the content is 'ff' in the trigger control register ($001f). user just clear control bits in this trigger register and switch these interrupts to falling edge triggered.
nt68p62 -01 20 control bit description addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w control register for polling interrupt - - - - - - inte0 intmute r $0016 nmipoll 00h - - - - - - clre0 clrmute w $0017 irqpoll 00h - - - - - irq2 irq1 irq0 r control registers of interrupt enable $0018 ienmi 00h - - - - - - inte0 intmute rw $0019 ieirq0 00h - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 rw $001a ieirq1 00h - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 rw $001b ieirq2 00h - - - - intadc intv inte1 intmr rw control registers for polling (read) & clearing (write) interrupt requests - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 r $001c irq0 00h - - clrs0 clra0 clrtx0 clrrx0 clrnak0 clrstop0 w - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 r - - clrs1 clra1 clrtx1 clrrx1 clrnak1 clrstop1 w $001d irq1 00h - - - - clradc clrv clre1 clrmr w selection of edge triggered for inte0 & 1 interrupt $001f trigger ffh - - - - - intvr inte1r inte0r r/w
nt68p62 -01 21 12. i/o ports the nt68p62 has 25 pins dedicated to input and output. these pins are grouped into 4 ports. 12.1. port0 : p00 - p07 port0 is an 8-bit bi-directional cmos i/o port with pmos as internal pull-up (figure 12.1). each pin of port0 may be bit programmed as an input or output port without software control the data direction register. when port0 works as output, the data to be output are latched to the port data register and output to the pin. p ort0 pins that have '1's written to them are pulled high by the internal pmos pull-ups. in this state they can be used as input, then the input signal can be read. this port output is high after reset. p00 - p05 are shared with dac7 - dac12 respectively. if endk7 - endk12 is set to low in endac register, p00 - p05 will act as dac7 - dac12 respectively (figure 12.2 ). after the chip is reset, endk7 - endk12 will be in the high state and p00 - p05s will act as i/o ports. p06 ?b p07 are shared with vsynco & hsynco respectively. if enhout ?b envout is set to low in hvcon register, p06 ?b p07 will act as vsynco & hsynco respectively (figure 12.3 ). after the chip is reset, enhout & envout will be in the high state and p06 ?b p07 will act as i/o pins. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $0000 pt0 ffh p07 p06 p05 p04 p03 p02 p01 p00 rw ffh - - hsynci vsynci hpoli vpoli hpolo vpolo r $0007 hv con ffh enhout envout - - - - hpolo vpolo w $000f endac ffh - - endk12 endk11 endk10 endk9 endk8 endk7 w v dd i/o data out data in figure 12.1. i/o structure pwm output pwm data in figure 12.2 . pwm output structure v dd o/p data out figure 12.3 . output structure
nt68p62 -01 22 12.2. port1: p10 - p16 port10 - port16 is a 7-bit bi-directional cmos i/o port with pmos as internal pull-up (figure 12.1 ). each bi- directional i/o pin may be bit programmed as an input or output port without software control the data direction register. when p ort 1 works as output, the data to be output is latched to the port data register and output to the pin. port 1 pins that have '1's written to them are pulled high by the internal pmos pull-ups. in this state they can be used as input, then the input signal can be read. this port output high after reset. p10 & p11 are shared with ad0 & ad1 input pins respectively. if the enadc0/ 1 bit in the enadc control register is cleared to low, a/d converters will activate simultaneously. after the chip is reset, enadc0/ 1 bits will be in the high state and p10 - p11 will act as i/o pins. p12 ?b p13 are shared with half signals input and output pins by accessing the outcon control register. if the enhalf bit is cleared to low, p13 will switch to halfhi pin (input pin) and p12 will switch to halfho pin (output pin, figure 12.3 ). for halfhi & halfho pin description, please refer half frequency function in the h/v sync processor paragraph. after the chip is reset, the enhalf bits will be in high state and p12 ?b p13 will act as i/o pins. p14 is shared with output pin of self test pattern. if users clear the pattern bit in the syncon control register and the free running function has been activated, the p14 will switch to output pin of the self test pattern. this pattern output pin is push-pull structure. after the chip is reset, pattern bits will be in the high state and p14 will act as i/o pin. (refer the 'syncprocessor' section for more detailed information.) p15 & p16 can be shared with external interrupt inte0 & inte1 pins if the inte0/1 bits are set in the control register of interrupt enable ($0016 & $0019). these interrupt pin have 'schmitt trigger' input buffers. after the chip is reset, inte0/1 bits will be in high state and p15 & p16 will act as i/o pin. refer 'interrupt controller' paragraph above for more details about the interrupt function. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $0001 pt1 7fh - p16 p15 p14 p13 p12 p11 p10 rw $000c freecon ffh enpat pat0 - - - freq2 freq1 freq0 w $0010 enadc ffh csta - - - enadc3 enadc2 enadc1 enadc0 w $0018 ienmi 00h - - - - - - inte0 intmute rw $001b ieirq2 00h - - - - - intv inte1 intmr rw data input i/p v dd figure 12.4 . schmitt input structure v dd i/o data out . data oe data in figure 12.5 . i/o structure
nt68p62 -01 23 12.3. p ort 2: p20 - p27 p ort 2, an 8-bit bi-directional i/o port (figure 12.5 ), may be programmed as an input or output pin by the software control. when setting the pt2dir control bit to '0', its correspondent pin will act as an output pin. on the other hand, clear pt2dir bit to '1', act as input pin. when programmed as an input, it has an internal pull-up resistor. when programmed as an output, the data to be output is latched to the port data register and output to the pin with push-pull structure. this port acts as input port after reset. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $0002 pt2dir ffh p27oe p26oe p25oe p24oe p23oe p22oe p21oe p20oe w $0003 pt2 ffh p27 p26 p25 p24 p23 p22 p21 p20 rw $0010 enadc ffh csta - - - enadc3 enadc2 enadc1 enadc0 w $0029 ch1con ffh enddc md1/ 2 srw start stop rxack txack - rw 12.4. p ort3 : p30 - p31 p ort3 is an 2 bit bi-directional open-drain i/o port (figure 1 2.6 ). each pin of p ort3 may be bit programmed as an input or output port with open drain structure. when p ort 3 works as output, the data to be output is latched to the port data register and output to the pin. w hen port 3 pins that have '1's written to them, users must connect port3 with external pulled-up resistor and then port3 can be used as input (the input signal can be read). this port output high after reset. p30 ?b p31 include schmitt trigger buffers for noise immunity and can be configured as the i 2 c pins sda0 & scl0 respectively. if set enddc to low in ch0ddc control register, p30 ?b p31 will act as sda0 & scl0 i/o pins respectively and will be an open drain structure (figure 1 2.6 ). after the chip is reset, this enddc bit will be in high state and port3 will act as i/o pins. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $0004 pt3 ffh - - - - - - p31 p30 rw $0029 ch1con ffh enddc md1/ 2 srw start stop rxack txack - rw i/o data out data in figure 1 2.6 . port3
nt68p62 -01 24 12.5. p ort4 : p40 - p41 port4 is available only on the 42pin sdip ic. port40 - port41 is an 2-bit bi-directional cmos i/o port with pmos as internal pull-up (figure 12.1 ). each bi-directional i/o pin may be bit programmed as an input or output port without software control the data direction register. when p ort 4 works as output, the data to be output is latched to the port data register and output to the pin. port 4 pins that have '1's written to them are pulled high by the internal pmos pull-ups. in this state they can be used as input. the input signal can be read. this port outputs high after reset. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $0005 pt4 ffh - - - - - - p41 p40 rw 13. h/v sync signals processor the functions of the sync processor include polarity detection, hsync & vsync signals counting, and programmable sync signals output. it also provides 3-sets of free running signals and special output of test pattern at burn-in process when activating the free running output function. the nt68p62 can properly handle either composite or separate sync signal inputs even without sync signal input. as to processing the composite sync signal, a hardware separator will be activated to extract the hsync signal under user controlled. the input at hsynci can be either a pure horizontal sync signal or a composite sync signal. for the sync waveform refer to figure 1 3.1 & figure 1 3. 2. the sync processor block diagram is shown in figure 13.3. both vsynci & hsynci pins have schmitt trigger and filtering process to improve noise immunity. any pulse that is shorter than 125 ns, will be regarded as a glitch and will be ignored. (a) positive polarity (b) negative polarity figure 13.1. separate h sync. waveform (a) positive polarity (b) negative polarity figure 13.2. composite h sync. waveform
nt68p62 -01 25 enable enable enable enable reset reset 8 us 16.384 ms enhsel control logic v sync. latch h sync. latch sync separator h hpoli vpoli v h hpolo vpolo h & v sync. polarity detector h sync. output control free_run control vsync input hsync input hsynco 0 1 1 0 vsynco hcntl hcnth digital filter vcntl vcnth s/c v 0 1 v schmitt trigger digital filter schmitt trigger h sync. counter v sync. counter v sync. output control s/c intv v 0 1 hsel 32.968 ms auto mute intmute freq0/1/2 pattern o/p control enpat, pat10/1 pattern figure 13.3. sync. processor block diagram
nt68p62 -01 26 13.1. v & h counter register: vcntl/h, hcntl/h vsync counter: vcntl/h, the 14-bit read only register, contains information of the vsync frequency. an internal counter counts the numbers of 8us pulse between two vsync pulses. when a next vsync signal is recognized, the counter is stopped and the vcnth/l register latches the counter value and then the counter counts from zero again for evaluating next vsync time interval. the counted data can be converted to the time duration between two successive vsync pulses by time 8 us. if no vsync incoming, the counter will overflow and set vcntov bit (in vcnth register) to high. once the vcntov set to high, it keeps in the high state until writing '1' to it (clrvov bit). hsync counter: if the enhsel bit is set to high, the internal counter counts the hsync pulses between two vsync pulses. the hcntl/h control registers contain the numbers of hsync pulse between two vsync pulses. these data can determine if the hsync frequency is valid or not to determine the accurate video mode. the system supports two other options of interval for user counting the frequency of hsync pulses. if users clear the enhsel and set the hsel bits properly, this internal counter counts the hsync pulses during this system defined time interval. the time interval is defined below: enhsel hsel hsync freq note 1 - disabled after system reset or users disabling 0 0 16.384 ms 0 1 32.768 ms after system reset, this interval will be disabled and the content of enhsel & hsel0 bits are '1'. when this function is disabled, the hcntl/h counter is working on the vsync pulse. it is invalid to write '00' to them. latching the hsync counter: the counted value will be latched by the hcnth/l register pairs which are updated by vsync pulse or system defined time interval. (refer the figure 13.4 for the opration of hcntl/h counter.) if the counter overflows, the hcntov bit (in hcnth register) will be set to high. once the hcntov is set to high, it keeps in the high state until writing '1' to it (clrhov bit). when setting this clrhov bit, the hcnt counter will not be reset to zero. hsynci vsynci ? ? ? latch hcnt register reset h sync. counter start pulse counting latch hcnt register reset h sync. counter start pulse counting ? ? ? hsynci ? ? ? 16.384ms/32.768ms (setting hsel0/1 bits) ? ? ? figure 13.4. hsync counter operation
nt68p62 -01 27 ? ? ? composite h sync. waveform (h eor v) (1) hsynci ? ? ? (2) hsynci composite h sync. waveform (h or v) ? ? ? 2 m s hsync pulse or no pulse, the output signal of hsync will be inserted. hsynco inserted hsync pulse vsynco original hsync pulse original hsync pulse widen 9 m s figure 13.5. composite h & v sync. processing
nt68p62 -01 28 vcntov = '1' ? hcnth = '00' ? no yes yes no read vcnt|hcnt counter register normal mode seperate sync. freq. calculating set s/c = '0' clear vcntov & hcntov open intv & clear intv flag vcntov = '1' ? no yes yes no return stand-by mode off mode worng mode yes no suspend mode return freq. calculating 1. extract hcntl/h 12 bit data 2. 12 bit data * vsync. freq. = hsync. freq. or 12 bits data/time interval (16.382 or 32.968 ms) 3. its reciprocal is hsync. time duration. 1. extract vcntl/h 14 bit data 2. 14 bits data * 8 u s = vsync. time duration 3. its reciprocal is vsync. freq. set s/c = '1' & ensel = ''0' & select time intrval (16.384 or 32.968ms) clear vcntov & hcntov delay 2 * time intelval normal mode composite sync. hcnth ='00' ? hcnth = '00' ? sync. mode processing intv ? no yes delay 132 ms delay 132 ms read vcnt|hcnt counter register system default: open intv & clear intv flag s/c = '1' & ensel = '1' figure 13.6. h & v sync. software control flow chart (for reference only)
nt68p62 -01 29 13.2. sync processor control register: polarity: the detection of hsync or vsync polarity is achieved by hardware circuit that samples the sync signal's voltage level periodically. users can read hpoli & vpoli bit from hvcon register, which bit = '1' represents positive polarity and '0' represents negative polarity. furthermore, users can read hsynci and vsynci bit in hvcon register to detect h & v sync input signal. users can control the polarity of h & v sync output signal by writing the appropriate data to the hpolo and vpolo bits in the hvcon register, '1' represents positive polarity and '0', negative polarity. composite sync: users have to determine whether the incoming signal is separate sync or composite sync and set s/ c & enhsel / hsel bit properly. if the input sync signal is composite, after set s/ c to '0', the sync separator block will be activated (please refer figure 13.5). at the area of vsync pulse, there can exist hsync pulses or not. for the output of hsync, users can active hardware to interpolate the hsync pulses in that area by clearing the insen bit. the width of these inserted pulses is 2us fixed and the time interval is the same as previous one. according to the last hsync pulse outside the vsync pulse duration, the hardware will arrange the interval of these hardware interpolated pulses. these inserted hsync pulse have 125 ns phase deviation maximum. the vsync pulse can be extracted by hardware from composite hsync signal, and the delay time of output vsync signal will be limited bellow 20ns. for inserting hsync pulse safely, the extracted vsync pulse will be widens about 9 m s. because evenly inserting the hsync pulse, the last inserted hsync pulse will have different frequency from original ones. system will not implement this insertion function , users must clear insen bit in the syncon control register to activate this function. after reset, s/ c & insen bits default value is high and clear the vcnt | hcnt counter latches to zero. sync output: in pin assignment, vsynco & hsynco represent vsync & hsync output which are shared with p06 & p07 respectively. if envout & enhout is set to '0' in hvcon register, p06 & p07 will act as vsynco & hsynco output pins. when the input sync is separate signal, the v/hsynco will output the same signal as input without delay. but if the input sync is composite signal, the vsynco signal will have fixed delay time about 20ns and the hsynco has nonfixed delay time about 125ns. half frequency input and output: in pin assignment, when users set enhalf bits to '0' in halfcon register, the halfho pin will act as output pin and output half of input signal in the halfhi pin with 50% duty (see figure 13.7). if set nohalf to '0', halfho will output the same signal in the halfhi pin and user can control its polarity of output halfho by setting halfpol bit, '1' for positive and '0' for negative polarity. after the chip is reset, enhalf ?b nohalf & halfpol will be in the high state and p12 & p13 will act as i/o pins. it is recommended to add a schmitt trigger buffer at front of the halfi pin. free run signal output: user can select one of free running frequency (list bellow) outputting to hysnco & vsynco pin by setting the freq0/1/2 bits. if user does not enable h/vsynco by clearing envout or enhout bits, any setting of freq0/1/2 bits will be invalid. after system reset, nt68p62 does not provide free running frequency and both of freq0/1/2 bits are set to ' 1'. the free running frequency can be set according the table below: free running freq. freq2 freq1 freq0 hsync freq. vsync freq. note 1 0 0 0 8m/256=31.2k hsync/512=61.0hz refer to figure 13.7 2 0 0 1 8m/4/9/5=44.4k hsync/512=86.8hz 3 0 1 0 8m/128=62.5k hsync/3/5/7/8=74.4hz 4 0 1 1 8m/4/5/5=80k hsync/1024=78.1hz 5 1 0 0/1 8m/4/2/11=90.9k hsync/1024=88.7hz 1 1 0 1 1 1 disabled free run function after system reset
nt68p62 -01 30 self testing pattern: at activating free running function, the system will generate the testing pattern when clearing the enpat bit. the port14 pin will switch from i/o pin to pattern output pin (push-pull structure). the system provides four types of testing patterns. refer the figure below. set the pat0 bits to select the pattern type (figure 13.8). if the free run function has not been enabled, any change of enpat & pat0 bits will be invalid. refer the figure 13.9 for the porch time of video pattern. pat0 test pattern note 0 (1) only activated on enpat bit be cleared 1 (2) the porch of self test pattern are listed below: free running freq. front porch of vblank back porch of vblank front porch of hblank back porch of hblank vsync pulse width hsync pulse width 1 128 m s 864 m s 460ns 2.00 m s 64 m s 1 m s 2 90.5 m s 589 m s 1.18 m s 1.93 m s 64 m s 1 m s 3 51 m s 528 m s 424ns 1.92 m s 64 m s 1 m s 4 51.5 m s 596 m s 185ns 1.94 m s 64 m s 1 m s 5 46.6 m s 515 m s 436ns 1.94 m s 64 m s 1 m s mode change detection: the system provides a hardware detection of sync signal changed and support user to respond to this transition an proper process as soon as possible. there are three kinds of detections to set intmute bit. hsync counter: users can enable hdiff comparison by clearing enhdiff bit and then preload an difference value to hdiff0-3 bits in the automute control register ($000e). the system will latch the new value of hsync counter and compare it with the last latched value. if this difference is great than this user defined value at hdiff0-3 bits, system will set the intmute interrupt bit. h/v polarity: users can enable polarity detection by clearing enpol bit. the system will set the intmute bit when the polarity of hsync or vsync have been changed. h/v counter overflow: users can enable the detection of sync counters overflow by clearing enover bit. the system will set the intmute bit whenever the counter of hsync or vsync has been overflowed. the above three sources of setting this intmute bit can be enabled or disabled by user. if user opens this interrupt, the system will generate an nmi interrupt to remind users anytime. at user's manipulation, a software debounce to confirm the transition of sync signal for one more times will make this system stable and reliable, but it will affect the response time. after system reset, this 'automute' function will be disabled and the hdiff0-2 control bits will be cleared to ' $0f'. halfhi halfho: half freq. output signal (50% duty) halfho output signal when nohalf bit clear to low (the same signal as in the halfhi pin) figure 13.7. half freq. sync. waveform
nt68p62 -01 31 (1) (2) figure 13.8. two types of testing pattern back-porch back-porch front-porch front-porch 64 m s vsync hsync 1 m s video video figure 13.9. the porch of free running self test pattern
nt68p62 -01 32 13.3 power saving mode detect: video mode is listed as below, especially from mode 2 to mode 4 just for power saving. all of modes can be detected by nt68p62 (figure 13.6). these modes can be easily be detected. mode h-sync v-sync (1) normal active active (2) stand-by inactive active (3) suspend active inactive (4) off inactive inactive control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w control registers for synprocessor ffh - - - - insen - hsel s/ c r $0006 syncon ffh - - - - insen enhsel hsel s/ c w ffh - - hsynci vsynci hpoli vpoli hpolo vpolo r $0007 hv con ffh enhout envout - - - - hpolo vpolo w $0008 hcnt l 00h hcl7 hcl6 hcl5 hcl4 hcl3 hcl2 hcl1 hcl0 r hcntov - - - hch3 hch2 hch1 hch0 r $0009 hcnt h 00h clrhov - - - - - - - w $000a vcnt l 00h vcl7 vcl6 vcl5 vcl4 vcl3 vcl2 vcl1 vcl0 r vcntov - vch5 vch4 vch3 vch2 vch1 vch0 r $000b vcnt h 00h clrvov - - - - - - - w $000c freecon ffh enpat pat0 - - - freq2 freq1 freq0 w $000d halfcon ffh enhalf nohalf halfpol - - - - - w $000e automute ffh enhdiff enpol enover - hdiffvl3 hdiffvl2 hdiffvl1 hdiffvl0 w
nt68p62 -01 33 14. base timer (bt) the base timer is an 8-bit counter, and its clock source can be chosen with 1 m s or 1ms by setting the btclk bit ('0' for 1 m s and '1' for 1ms). the bt can be enabled or disabled by the enbt bit in the btcon register. the bt will start counting while clearing the enbt bit to ? 0 ? . after the chip is reset, the btclk and enbt bits are set to '1' (the b t is disabled). before enabling the b t , it can be preloaded with a value by writing a value to the bt register (write only) at any time and then the b t will start to count up from this preloaded value. when the bt ? s value reaches ffh, it will generate a timer interrupt if the timer interrupt is enabled, and then the counter will wrap around to 00h. the timer ? s maxium interval is 256ms or 256 m s depending on the btclk value. bt7 intmr int 1us 1ms btclk 1 0 bt6 bt5 bt4 bt3 bt2 bt1 bt0 control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w $002e bt 00h bt7 bt6 bt5 bt4 bt3 bt2 bt1 bt0 w $002f bt con 03h - - - - - - btclk enbt w
nt68p62 -01 34 15. i 2 c bus interface: ddc1 & ddc2b slave mode interface: i 2 c bus interface is a two-wire, bi-directional serial bus which provides a simple, efficient way for data communication between devices, and minimizes the cost of connecting among various peripheral devices. nt68p62 provides two i 2 c channels. both of them are shared with i/o pins and their structures are open drain. when the system is reset, these channels are originally general i/o pins structure. all of these i 2 c bus function will be activated only after their enddc bits are cleared to '0' (ch0/1con registers). ddc1 & ddc2b+ function: two modes of operation have been implemented in nt68p62, uni-directional mode (ddc1 mode) and bi-directional mode (ddc2b+ mode). these channels will be activated as ddc1 function initially when users enable ddc function. these channels will switch automatically to ddc2b+ function from ddc1 function when a low pulse greater than 500ns is detected on the scl line. users can start a master communication directly from ddc1 communication by clearing mode bit in the ch0/1clk control register. the channels can return to ddc1 function when users set the md1/ 2 bit to '1' in the ch0/1con registers. 15.1. ddc1 bus interface vsync input and sda pin: in ddc1 function, the vsync pin is used as input clock pin and sda pin is used as data output pin. this function comprises two data buffers: one is preloading data buffer for putting one byte data in advance by user (ch0/1txdat), and the other is shift register for shifting out one bit data to sda line, which users can not access directly. these two data buffer cooperate properly. for the timing diagram please refer to figure 15.1. after system resets, the i 2 c bus interface is in ddc1 mode. data transfer: at first, user must put one byte transmitted data into ch0/1txdat register in advance, and activate i 2 c bus by setting enddc bit to '0'. then open inttx0/1 interrupt source by setting inttx0/1 to '1' in the ieirq0/1 registers. on the first 9 rising edges of vsync, system will shift out invalid bit in shift register to sda pin to empty shift register. when shift register is empty and on next rising edge of vsync, it will load data in the ch0/1txdat registers to internal shift register. at the same time, nt68p62 will shift out msb bit and generate an inttx0/1 interrupts to remind user to put next byte data into ch0/1txdat register. after eight rising clocks, there have been eight bits shifted out in proper order and shift register becomes empty again. at the ninth rising clock, it will shift the ninth bit (null bit '1') out to sda. and on the next rising edge of vsync clock, system will generate an inttx0/1 interrupts again. by the same way, nt68p62 will load new data from ch0/1txdat registers to internal shift register and shift out one bit right away. beware that user should put one new data into ch0/1txdat registers properly before the shift register is empty (the next inttx0/1 interrupt). if not, the hardware will tansmit the last byte data repeatedly. vsync clock: only in the separate sync mode, can the vsync pulse be used as data transfer clock, its frequency can be up to 25khz maximum. in composite vsync mode, nt68p62 can not transmit any data to sda pin, regardless whether the vsync can be extracted from composite hsync signal.
nt68p62 -01 35 control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w - - - - - - inte0 intmute r $0016 nmipoll 00h - - - - - - clre0 clrmute w $0017 irqpoll 00h - - - - - irq2 irq1 irq0 r $0019 ieirq0 00h - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 rw $001a ieirq1 00h - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 rw - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 r $001c irq0 00h - - clrs0 clra0 clrtx0 clrrx0 clrnak0 clrstop0 w - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 r $001d irq1 00h - - clrs1 clra1 clrtx1 clrrx1 clrnak1 clrstop1 w control register for ddc1/2b+ of channel 0 $0021 ch0addr a0h adr7 adr6 adr5 adr4 adr3 adr2 adr1 - w $0022 ch0txdat 00h tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 w $0023 ch0rxdat 00h rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 r md1/ - start stop - txack - w $0024 ch0con e0h - - start stop rxack - - r $0025 ch0clk ffh - - ddc2br2 ddc2br1 ddc2br0 w control register for ddc1/2b+ of channel 1 $0026 ch1addr a0h adr7 adr6 adr5 adr4 adr3 adr2 adr1 - w $0027 ch1txdat 00h tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 w $0028 ch1rxdat 00h rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 r md1/ - start stop - txack - w $0029 ch1con e0h - - start stop rxack - - r $002a ch1clk ffh - - ddc2br2 ddc2br1 ddc2br0 w
nt68p62 -01 36 (in ch0con register) ? ? second byte data first byte data user can load next byte data to ch0txdat register load data in the ch0txdat register to shift register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 15.1. ddc1 mode timing diagram 15.2. ddc2b + slave & master mode bus interface the built-in ddc2b+ i 2 c bus interface features as follows ?g - slave mode (nt68p62 is addressed by a master which drives scl signal) - master mode (nt68p62 addresses external device and send out scl clock) - compatible with i 2 c bus standard - one default address (a0h) and one programable address - automatic wait state insertion - interrupt generation for status control - detection of start and stop signals the ddc2b+ will be activated as slave mode initially. users can switch to master mode by clearing the bit under either of these conditions listed as follows: 1. after entering to ddc1 function and clearing this bit, the system will be changed from ddc1 to ddc2b+ master mode operation. 2. after entering to ddc2b+ slave mode function and clearing this bit, the system will changed from slave mode into master mode operation. as clearing bit, system will send out a 'start' condition and wait for user to put the calling address into ch0/1txdat control register. notice that user must predetermine the direction of master mode transmission before putting calling address. below is the ddc2b+ function with channel 0, and the manipulation of channel 1 is the same as channel 0.
nt68p62 -01 37 ? ? ? ? ? condition condition ? figure 15.2. ddc2b data transfer
nt68p62 -01 38 (external device) (b) write mode timing diagram (a) write mode data format data transferred from external device from external device to nt68p62 from nt68p62 to external device a = acknowledge figure 15.3. ddc2b write mode spec .
nt68p62 -01 39 (external device) (b) read mode timing diagram (a) read mode data format from external device to nt6862 from nt6862 to external device a = acknowledge a = no acknowledge data transferred from nt6862 nt68p62 address user load first data into txdat buffer figure 15.4. ddc2b read mode spec .
nt68p62 -01 40 15.3. ddc2b slave mode bus interface enable i 2 c and ints: after user clears the to ? 0 ? , nt68p62 will enter into ddc1 mode, and it will switch to ddc2b slave mode while a low pulse is detected on scl line. the ddc2b bus consists of two wires, scl and sda; scl is the data transmission clock and sda is the data line. nt68p62 will remind user that the mode has changed by generating a ints interrupt. when users set md1/ to '1' at this time, the nt68p62 will return back to ddc1 mode. (for ddc2b please refer to figure 15.2.) the figure exhibits what are important in i 2 c: start signal, slave address, transferred data (proceed byte by byte) and a stop signal. start condition: when scl & sda lines are at high state, an external device (master) may initiate communication by sending a start signal (defined as sda from high to low transition while scl is at high state). when there is a start condition, nt68p62 will set the 'start' bit to '1' and user can poll this status bit to control ddc2b transmission at any time. this bit will keep '1' until user clears it. after sending a start signal for ddc2b communication, an external device can repeatedly send start condition without sending a stop signal to terminate this communication. this is used by external device to communicate with another slave or with the same slave in different mode (read or write mode) without releasing the bus. address matched and inta0: after the start condition, a slave address is sent by an external device. when i 2 c bus interface changes to ddc2b mode, nt68p62 will act as a receiver first to receive this one byte data. this address data is 7 bits long followed by the eighth bit (r/w) that indicates data transfer direction. when the nt68p62 system receives an address data from an external device, it will store it in the ch0rxdat register. the system supports 'a0' default address and another one set of addresses which can be accessed by writting the ch0addr register. upon receiving the calling address from an external device, the system will compare this received data with the default 'a0' address and data in the ch0addr register. either of these address matched, the system will set the inta0 bit in the irq0 register. if the user sets inta0 bit to '1' (in ieirq0 register) in advanced and addresses match, the nt68p62 will generate a inta0 interrupt. under the address matching condition, the nt68p62 will send an acknowledge bit to an external device. if address does not match, the nt68p62 will not generate inta0 interrupt and neglect the data change on sda line in the future. data transmission direction: in inta0 interrupt servicing routine, user must check the lsb of address data in ch0rxdat register. according to i 2 c bus protocol, this bit indicates the ddc2b data transfer direction in later transmission; '1' indicates a request for 'read mode' action (external master device read data from system), '0' indicates a 'write mode' action (external master device write data to system). the timing about read mode and write mode please refer to figure 15.3 and figure 15.4. the data transfer can proceeded byte by byte in a direction specified by the r/ bit after a successful slave address is received. the system will switch to either 'read' mode or 'write' mode automatically which is determined by this direction bit. figure 15.5. ddc structure block txdat txack 9 bits shift register compare logic addr rxdat inta enddc in out clk inttx intrx intnak ddc2br [2 ..0] clock generator sda vsync scl ints mode md1/2 r/w stop detector intstop
nt68p62 -01 41 data transfer and wait: the data on the sda line must be stable during the high period of the clock on the scl line. the high and low state of the sda line can only change when the clock signal on the scl line is low. each byte data is eight bits long and one clock pulse for one bit of data transfer. data is transferred with the most significant bit (msb) first. in the wired-and connection, any slower device can hold the scl line low to force the faster device into a wait state. data transmition will be suspended until the slower device is ready for the next byte transfer by releasing the scl line. acknowledge: the acknowledgment will be generated at ninth clock by whom receiving data. in the write mode, nt68p62 system must respond to this acknowledgment. users should clear the bit in the ch0con to open the ? ack ? function. after receiving one byte data from external device, nt68p62 will automatically send this acknowledgment bit. in the read mode, an external device must respond to the acknowledgment bit after every byte data is sent out. the system will set the intnak bit when external device does not send out the '0' acknowledgment bit. furthermore, user can open this interrupt source by clearing the intnak bit in the ieirq0 register. the inttx0 & intrx0 interrupt: after nt68p62 complete one byte transmission or receiving, it will generate an inttx0 (read mode) & intrx0 (write mode) interrupts. these interrupts are generated at the falling edge of the ninth clock. users can control the flow of ddc2b transmission at these interrupts. the intrx0 on the write mode: nt68p62 read data from external master device. when users detect an intrx0 interrupt, it means there has one byte data received and user can read out by accessing ch0rxdat control register. at the same time, if user responded an 'ack' signal beforehand, the shift register will send out this 'ack' bit (low voltage) and continue to receive the next byte data. if both of shift register and ch0rxdat register are full and user still did not load data from ch0rxdat register, the scl will be held low and waiting for nt68p62. after user obtains one byte data from ch0rxdat register, the scl will be released for generation of scl transmission clock. external device can continue sending next byte data to nt68p62. the timing diagram refers to figure 15.3. user must responde a nak signal in advance to stop the transmission. the inttx0 on the read mode: external device read data from nt68p62. at inttx0 interrupt, the system will load new data from ch0txdat register which has been put by user beforehand into internal shift register and continue sending out this new data. after this new loading data be shifted out according every scl clock, system will request user to put next byte data into ch0txdat register. if both of shift register and ch0txdat register are empty and user still not load data to ch0txdat register, the scl will be held low and waiting by nt68p62 after receiving the acknowledgment bit. at scl holded low by system, after user has put one new byte data into ch0txdat register, the scl will be released for generation of scl transmission clock. at this time, system will load this byte data into shift register and generate a inttx0 interrupt again to remind user putting next byte into ch0txdat register. the timing diagram refer to figure 15.4. after every one byte data transfer, system will monitor if external master device has sent out this acknowledgment bit or not. if not, system will set the intnak bit (the acknowledgment is low signal). users will get a intnak interrupt if intnak has been enabled as a interrupt source. stop condition: when scl & sda line have been released (hold on 'high' state), ddc2b data transfer is always terminated by a stop condition generated by external device. a stop signal is defined as a low to high transition of sda while scl is at high state. when there is a stop condition, nt68p62 will set the 'stop' bit & intstop bit to '1' and user can poll this status bit or open a intstop interrupt to control ddc2b transmission at any time. this bit will keep '1' until user clears it by writing '1' to this bit. notice the scl and sda lines must conform to i 2 c bus specifications. for the software flowchart can please refer figure 15.6. please refer to the standard i 2 c bus specification for details. change to ddc1 mode: after an external device terminates ddc2 transmission by sending a stop condition, users can set md1/ to '1' for changing to ddc1 mode. on the other hand, when the scl line has been released (pulled- up), user can force nt68p62 to ddc1 mode communication at any time.
nt68p62 -01 42 irq0/1 group service routine change to ddc2 slave mode & receiving mode put slave addr. into intrx, intnak put one byte data into ch0txdat reg. read out the srw bit reset buffer index inttx & ints put one byte ch0txdatreg. ddc1 mode (md_con = 1) read one byte ch0rxdat reg. put $ff into ch0txdat reg. (release sda line) inttx, intnak & inta & intv intrx, intnak & inttx, intnak system release scl & sda & send out stop condition user can do some process transmission failed slave mode operation figure 15.6. slave mode int operation
nt68p62 -01 43 15.4 ddc2b+ master mode bus interface most of the ddc manipulation is the same as slave mode except the scl clock generation. in the master mode, the control of scl clock source belongs to nt68p62. users must set the calling address and transmission direction in advance. access the & bits to control the transmission flow of ddc2b+ master mode communication. start condition: after user clearing & bit, the system will generate a 'start' condition on the scl & sda lines and wait for user to put the calling address into txdat buffer and send to sda line. the frequency of scl is dependant on the baud-rate setting value (ddcbr0 - ddcbr2) in register ch0clk. and the data transmission direction will be dependant on the bit and the lsb of calling address, '1' for read operation and '0' for write operation. calling address: calling address is 8 bits long. it should be put in the ch0txdat. the setting of lsb bit in this txdat buffer should be as same as bit. stop condition: there are several cases that the system will send out 'stop' condition on the scl & sda lines. first, in the 'read' operation, if user sets txack bit to '1', the system will send out 'nak' condition on the bus after receiving one byte data and then send out 'stop' condition automatically later. second, in the 'start' condition and after sending out calling address, if no slave has respond to a 'ack' signal, the master will send out 'stop' condition automatically. third, if user sets bit to '1', the system will generate a 'stop' condition after the current byte transmission is done. notice that if slave device did not released scl and sda line, the system can not send out 'stop' condition. after 'stop' condition, the master will release scl & sda lines and return to slave mode. the inttx0 & intrx0 interrupt: after nt68p62 completing one byte transmission or receiving, it will generate an inttx0 (write mode) & intrx0 (read mode) interrupts. users can control the flow of ddc2b transmission at these interrupts. the intrx0 on the read mode: nt68p62 reads data from external slave device. when users detect a intrx0 interrupt, it means there is one byte data received and user can read out by accessing ch0rxdat control register. at the same time, if the user responded an 'ack' signal beforehand, the shift register will send out an 'ack' bit (low voltage) and continue to receive next byte data. if both the shift register and ch0rxdat register are full and user still did not load data from ch0rxdat register, the scl will be held low and wait for nt68p62. after user has received one byte data from ch0rxdat register, the scl will be released for generation of scl transmission clock. an external device can continue sending next byte data to nt68p62. refer figure 15.7 for the timing diagram. user must respond to a nak signal in advance to stop the transmission. before the last two bytes of data is received, user should respond an 'nak' signal. then, system will send out 'nak' bit after receiving the last byte data and 'stop' condition to notify the slave terminated current transmission. the inttx0 on the write mode: external device read data from nt68p62. at inttx0 interrupt, the system will load new data from ch0txdat register which has been put by user beforehand into internal shift register and continue sending out this new data. after this new loading data be shifted out according every scl clock, system will request user to put next byte data into ch0txdat register. if both of shift register and ch0txdat register are empty and user still not load data to ch0txdat register, the scl will be held low and wait for nt68p62 after receiving the acknowledgment bit. if scl is held low by system, and user has put one new byte data into ch0txdat register, the scl will be released for generation of scl transmission clock. at this time, system will load this byte data into shift register and generate an inttx0 interrupt again to remind user putting next byte into ch0txdat register. refer to figure 15.8 for the timing diagram. repeat start condition: if clearing the bit to '0' in the ' write' operation, system will send out a ' repeat start '. notice that if slave device did not release scl and sda line, the system can not send out 'repeat start condition. scl baud rate selection: there are three baud rate bits for user to select one of eight clock rates on the scl line. after system reset, the default value of these baud rate bits (ddc2br0-2) are '111'.
nt68p62 -01 44 ddc2br2 ddc2br1 ddc2br0 baud rate 0.00 0.00 0.00 400k 0.00 0.00 1.00 200k 0.00 1.00 0.00 100k 0.00 1.00 1.00 50k 1.00 0.00 0.00 25k 1.00 0.00 1.00 12.5k 1.00 1.00 0.00 6.25k 1.00 1.00 1.00 3.125k (external device putting data) figure 15.7. ddc2b+ master read mode timiing 1 2 3 4 5 6 7 8 if user read out first byte data from rxdat buffer, system will respond ack, nak or repeat start before user reads out this byte data from rxdat buffer, he can set txack = 1 to terminate communication 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 wait for user to put calling address into txdat buffer if user does not read out this byte data from rxdat buffer, the shift register will wait after receiving next byte data
nt68p62 -01 45 (external device) figure 15.8. ddc2b+ master write mode timing wait for user putting calling address into txdat buffer 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 if user wants to terminate this communication, he can set mode = 1 to send out stop condition or clear rstart = 0 to send out repeat start system will wait if user didn't send out the first byte data. as user loaded one byte data into txdat buffer, system will latch to shift register and send out msb bit after sending out first byte data, user will get another inttx to put next byte data into txdat buffer, if user does not send out the second byte data, the system will wait again after shifted out first byte data.
nt68p62 -01 46 control register: addr register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w control register for polling interrupt groups - - - - - - inte0 intmute r $0016 nmipoll 00h - - - - - - clre0 clrmut e w $0017 irqpoll 00h - - - - - irq2 irq1 irq0 r control registers of interrupt enable $0018 ienmi 00h - - - - - - inte0 intmute w $0019 ieirq0 00h - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 w $001a ieirq1 00h - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 w $001b ieirq2 00h - - - - - intv inte1 intmr w control registers for polling interrupt requests - - ints0 inta0 inttx0 intrx0 intnak0 intstop0 r $001c irq0 00h - - clrs0 clra0 clrtx0 clrrx0 clrnak0 clrstop0 w - - ints1 inta1 inttx1 intrx1 intnak1 intstop1 r $001d irq1 00h - - clrs1 clra1 clrtx1 clrrx1 clrnak1 clrstop1 w - - - - intadc intv inte1 intmr r $001e irq2 00h - - - - clradc clrv clre1 clrmr w control register for ddc1/2b+ of channel 0 $0021 ch0addr a0h adr7 adr6 adr5 adr4 adr3 adr2 adr1 - w $0022 ch0txdat 00h tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 w $0023 ch0rxdat 00h rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 r md1/ - start stop - - w $0024 ch0con e0h - - start stop - - - r $0025 ch0clk ffh - - ddc2br2 ddc2br1 ddc2br0 w control register for ddc1/2b+ of channel 1 $0026 ch1addr a0h adr7 adr6 adr5 adr4 adr3 adr2 adr1 - w $0027 ch1txdat 00h tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 w $0028 ch1rxdat 00h rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 r md1/ - start stop - - w $0029 ch1con e0h - - start stop - - r $002a ch1clk ffh - - ddc2br2 ddc2br1 ddc2br0 w
nt68p62 -01 47 last comm, is repeat start? send address open inttx intnak reset buffer index master receiver recev. over? send address send repeat start set last byte flag open intrx & intnak one byte data? after recv. data send repeat start? send no_ack set last byte flag send no_ack set last byte flag mode = 0 send address open inttx & intnak send address send repeat start set last byte flag open inttx & intnak one byte data? after recv. data send repeat start? figure 15.9. master receiver operation figure 15.10. master transmitter operation last comm, is repeat start? send address send repeat start open inttx intnak reset buffer index master transmitter trans. over? mode = 0 send address open inttx & intnak
nt68p62 -01 48 irq0/1 group service routine open intrx & intnak int read one byte receiver over close int interrupt read one byte send repeat start set last byte flag write 1 to mode bit (system send out a stop) send repeat start close int interrupt figure 15.11. master mode int operation send repeat start set last byte flag read one byte write 1 to mode bit (system send out a stop) put next byte data ch0txdatreg. open intrx & intnak int other interruptprocess or have someerror no slave device exist system will send outstop & set mode bit to 1 automatically transmission failed
nt68p62 -01 49 user referenced flow chart comparison with nt68p61a item nt68p61a status nt68p62 status notes maximum rom size 24k bytes 32k bytes ram size 256 bytes 512 bytes pwm channel 14 channels 5v & 12v open drain o/p 13 channels 5v open drain o/p only pwm channel refresh rate 31.25 khz 62.5 khz a/d converter channel 2 channels 4 channels 6 bit resolution v counter bit no. 12 bits (handle vsync freq. down to 30.5hz) 14 bits (handle vsync freq. down to 7.6hz) h interval 8.192 ms 16.384 & 32.768 ms auto mute x o free run freq. 2 sets 5 sets self test pattern x o 2 self test patterns iic bus channel 1 channel 2 channels iic bus baud rate max 100khz max 400khz iic mode supported ddc1/2b ddc1/2b+ external interrupt 1 set 2 sets nmi interrupt x o interrupt trigger edge programmable x o mask rom option 4k/8k/16k/24k 24k/32k
nt68p62 -01 50 dc electrical characteristics (v dd = 5v, t a = 25 c, oscillator freq. = 8mhz, unless otherwise specified) symbol parameter min. typ. max. unit conditions i dd operating current 20 ma no loading v ih1 input high voltage 2 v p00-p07, p12-p16, p20-p27, p40, p41 , vsynci, hsynci, halfhi inte0, inte1 v ih2 input high voltage 3 v scl0/1, sda0/1,p10, p11, p30, p31 pins v il1 input low voltage 0.8 v p00-p07, p12-p16, p20-p27, p40, p41 , vsynci, hsynci, halfhi, inte0, inte1 v il2 input low voltage 1.5 v scl0/1, sda0/1, p10, p11 p30 ,p31 pins i ih input high current -200 -350 m a p00-p07, p10-p16, p20-p27, p40,p41 vsynci, hsynci, halfhi, (v ih =2.4v); v oh1 output high voltage 2.4 v p00-p07, p10-p16, p40, p41 (i oh = -100 m a) vsynco, hsynco (i oh = -4ma) halfho (i oh = -4ma) pattern, p20-p27 (i oh = -10ma) v oh2 output high voltage (dac0-dac12) 5 v external applied voltage v ol output low voltage 0.4 v p00-p07, p10-p16, p40, p41, dac0-12 (i ol = 4ma) scl0/1, sda0/1 (i ol = 5ma) vsynco, hsynco (i ol = 4ma) halfho (i ol = 4ma) pattern, p20-p27 ( i ol = 10ma) r ol pull down resistor ( ) 50 100 150 k w r oh1 pull up resistor ( inte0, inte1) 11 22 33 k w r oh2 pull up resistor ( port0, port1, & port4 ) 11 22 33 k w r oh3 pull up resistor ( hsynci & vsynci & halfi ) 11 22 33 k w
nt68p62 -01 51 ac electrical characteristics (v =5v, t =25 c, oscillator freq.=8mhz, unless otherwise specified) symbol parameter min. typ. max. unit conditions fsys system clock 8 mhz t cnvt a/d conversion time 750 m s voffset a/d converter error 1 lsb vlinear a/d input dynamic range of linearity conversion 1.5 3.5 v t delay the delay time of vsync input and vsync output 20 ns composite sync with fixed delay (refer figure 13.5) t reset reset pulse width low 2 t cycle t cycle = 2/ fsys fvsync vsync input frequency 25k hz t vsync = 1/fvsync t vpw vsync input pulse width 8 2000 m s fhsync hsync input frequency 120 khz t hsync = 1/fhsync t hpw1 maximum pulse width of hsync input high (positive polarity) 0.25 7 m s t hpw2 minimum pulse width of hsync input low (positive polarity) 9.125 m s t error1 counting deviation of base timer 1 m s 1 m s clock source t error2 counting deviation of base timer 1 ms 1ms clock source
nt68p62 -01 52 ddc1 mode symbol parameter min. typ. max. unit conditions t vpw vsync high time 0.50 2000 m s fvsync vsync input frequency 25k hz t vsync =1/fvsync t dd data valid 200 500 ns t mode time for transition to ddc2b mode 500 ns vsync output ?
nt68p62 -01 53 ddc2b+ mode symbol parameter min. typ. max. unit f scl scl clock frequency 400 khz t buf bus free between a stop and start condition 4.7 m s t hd ; sta hold time for start condition 0.8 m s t low low period of the scl clock 1.3 m s t high high period of the scl clock 0.8 m s t su ; sta set-up time for a repeated start condition 1.3 m s t hd ; dat data hold time 200 ns t su ; dat data set-up time 300 ns t r rise time of both sda and scl signals 1 m s t f fall time of both sda and scl signals 300 ns t su ; sto set-up time for stop condition 0.80 m s
nt68p62 -01 54 ordering information part no. packages nt68 p62 40l p-dip nt68 p62 u 42l s-dip
nt68p62 -01 55 package information p-dip 40l outline dimensions unit: inches/mm seating plane symbol dimensions in inches dimensions in mm a 0.210 max. 5.33 max. a 1 0.010 min. 0.25 min. a 2 0.1550.010 3.940.25 b 0.018 +0.004 0.46 +0.10 -0.002 -0.05 b 1 0.050 +0.004 1.27 +0.10 -0.002 -0.05 c 0.010 +0.004 0.25 +0.10 -0.002 -0.05 d 2.055 typ. (2.075 max.) 52.20 typ. (52.71 max.) e 0.6000.010 15.240.25 e 1 0.550 typ. (0.562 max.) 13.97 typ. (14.27 max.) e 1 0.1000.010 2.540.25 l 0.1300.010 3.300.25 a 0 ~ 15 0 ~ 15 e a 0.6550.035 16.640.89 s 0.093 max. 2.36 max. notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash.
nt68p62 -01 56 package information s-dip 42l outline dimensions unit: inches/mm seating plane symbol dimensions in inches dimensions in mm a 0.200 max. 5.08 max. a 1 0.020 min. 0.51 min. a 2 0.157 max. 4.0 max. b 0.051 max. 1.3 max. 0.031 min. 0.8 min. b 1 0.021 max. 0.53 max. 0.016 min. 0.40 min. c 0.013 max. 0.32 max. 0.010 min. 0.23 min. d (1) 1.531 max. 38.9 max. 1.512 min. 38.4 min. e (1) 0.551 max. 14.0 max. 0.539 min. 13.7 min. e 0.070 1.778 e 1 0.600 15.24 l 0.126 max. 3.2 max. 0.114 min. 2.9 min. m e 0.622 max. 15.80 max. 0.600 min. 15.24 min. m h 0.675 max. 17.15 max. 0.626 min. 15.90 min. w 0.007 0.18 z (1) 0.068 max. 1.73 max. notes: 1. plastic or metal protrusions of 0.25 mm maximu m per side are not included.

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